Mr. Jiandong Ma, Chinese Academy of Sciences, China
Mr. Jiandong Ma is a dedicated researcher based in Beijing, currently pursuing a Ph.D. in Signal and Information Processing at the University of Chinese Academy of Sciences (UCAS). He has a strong educational background, having completed his Bachelor’s degree in Network Engineering at the University of Electronic Science and Technology of China (UESTC). With extensive experience in leading projects focused on advanced FPGA solutions, Jiandong has made significant contributions in the development of Remote Direct Memory Access (RDMA) technologies, particularly in out-of-order (OOO) packet transmission and packet reordering systems for multipath networks. His innovative work has led to several patents, reflecting his expertise in hardware packet processing and network optimization. In addition to his technical achievements, Jiandong has published multiple research papers in reputable journals and has been recognized as a Merit Student at his university. His commitment to scientific advancement is also evident in his volunteer work at public science events, showcasing his passion for knowledge sharing and community engagement.
Professional Profile:
ORCID
Suitability of Jiandong Ma for the Best Researcher Award
Jiandong Ma is a prominent candidate for the Best Researcher Award due to his outstanding academic qualifications, leadership in innovative research projects, significant contributions to his field, and recognition through patents and publications.
🎓 Education
- Ph.D. in Signal and Information Processing
University of Chinese Academy of Sciences (UCAS)
🏫 School of Electronic, Electrical and Communication Engineering
- Bachelor of Engineering in Network Engineering
University of Electronic Science and Technology of China (UESTC)
🏫 Yingcai Honors College
💼 Work Experience
- Team Leader
FPGA – Out-of-Order (OOO) RDMA NIC
- Led a team to develop a Gbps RDMA NIC supporting OOO packets via Xilinx ERNIC IP.
- Improved WQE transmission performance significantly under multipath scenarios.
- Supported dynamic resource management and selective retransmission.
- Team Leader
FPGA – Packet Reordering and Deduplication System
- Developed a system for multipath SD-WAN, achieving substantial space usage reduction and Gbps throughput.
- Developer
FPGA – Deep Flow Table
- Developed an exact match table with millions of entries using DDR, ensuring flexible entry space management.
- Optimizer
DPDK – DDoS Filter Unit and SDN Switch Multi-core Performance
- Optimized data structures for multi-core performance expansion of SDN switches and filtered DDoS traffic.
🏆 Achievements
- Patents:
- A method and system for out-of-order direct write in RDMA (Received)
- A bitmap-based out-of-order packet reception method for RDMA (Received)
- A sliding window-based RDMA transmission method and system (Received)
- A network packet deduplication and reordering system (Primary Check Passed)
- An IP whitelist-based method for filtering DDoS traffic (Granted)
- A method and system for managing variable-length key-value entries (Granted)
- Papers:
- SSPRD: A Shared-Storage-Based Hardware Packet Reordering and Deduplication System for Multipath Transmission in Wide Area Networks (SCI, accepted)
- ORNIC: A High-Performance RDMA NIC with Out-of-Order Packet Direct Write Method for Multipath Transmission (SCI, accepted)
🎖️ Awards and Honors
- Merit Student of the University
- Volunteer at the Academy of Sciences Public Science Day
Publication Top Notes:
ORNIC: A High-Performance RDMA NIC with Out-of-Order Packet Direct Write Method for Multipath Transmission
SSPRD: A Shared-Storage-Based Hardware Packet Reordering and Deduplication System for Multipath Transmission in Wide Area Networks